1. Field of the Invention
The present invention relates generally to a signal processing circuit, and more particularly, to an improved signal processing circuit that processes signals by sampling data from a plurality of channels at different selected sampling frequencies.
2. Description of the Related Art
Digitization of audio recording/reproduction apparatuses capable of editing audio data has proceeded briskly in recent years. In the digital audio field, digital data is typically processed in 16-bit chunks, as typified by the compact disk, or CD.
FIG. 1 is a block diagram of a conventional digital signal recording/reproduction apparatus.
As shown in FIG. 1, the conventional digital recording and/or reproduction apparatus (hereinafter recording/reproduction apparatus) 1 comprises a signal processing component 2, a read/write component 3 and an operation control component 4. The signal processing component 2 in turn comprises an analog/digital (A/D) converter 11, a digital audio circuit component 12, a digital/analog (D/A) converter 13 and a PLL circuit component 14.
A two-channel (left channel and right channel) analog signal is supplied from an input terminal to the A/D converter 11, together with a channel switching clock LRCK and a serial data clock SCLK from the PLL circuit component 14.
The A/D converter 11 selects the converted digital data from one or the other of the L channel or the R channel depending on the LR switching clock LRCK. The digital data converted by the A/D converter 11 is then supplied to the digital audio circuit component 12. The digital audio circuit component 12 processes the digital data supplied from the A/D converter 11 and supplies the processed data to the read/write component 3.
The read/write component 3, for example, comprises a hard disk drive, and records the digital data from the digital audio circuit component 12. The digital data written to the read/write component 3 is then read out, that is, reproduced, in response to a read command from the operation control component 4.
The digital data reproduced from the read/write component 3 is supplied to the digital audio circuit component 12. The digital audio circuit component 12 then processes the digital data from the read/write component 3 and supplies the processed data to the D/A converter 13.
The D/A converter 13 is supplied with the serial data clock SCLK and channel switching clock LRCK from the PLL circuit component 14. The D/A converter 13 acquires the digital data in a timing sequence set by the serial data clock SCLK and converts the acquired data into analog signals. The D/A converter 13 selects either L channel or R channel digital data based on the channel switching clock LRCK, and converts the selected data into an analog signal. The L channel or R channel analog signal output from the D/A converter 13 is then output from the L channel output terminal TLOUT or the R channel output terminal TROUT.
FIG. 2 is a diagram illustrating the operation of a conventional signal processing circuit, showing the timing of the channel switching clock LRCK, the serial data clock SCLK, and the digital data.
As shown in the diagram, the channel switching clock LRCK is set to a high level/low level duty ratio of 50:50. The A/D converter 11 selects the digitized analog signal from the L channel input terminal TLIN when the channel switching clock LRCK is high and selects the digitized analog signal from the R channel input terminal TRIN when the channel switching clock LRCK is low.
The serial data clock SCLK contains 64 clock cycles, or bits, for each cycle of the channel switching clock LRCK. Since the channel switching clock LRCK is set to a duty ratio of 50:50, the high level interval and the low level interval are each set to 32 bits of the serial data clock SCLK, respectively.
The digital data is output at a rate corresponding to 1 bit of data per 1 clock cycle or bit of the serial data clock SCLK. Moreover, although FIG. 2 illustrates a process of converting 24-bit digital data, the channel switching clock LRCK and serial data clock SCLK are capable of converting a maximum of 32-bit digital data.
However, recent efforts to further improve audio quality have lead to the development of high-frequency sampling. In order to effect such large-bit, high-frequency sampling, it is not enough simply to increase the number of digital data bits and increase the frequency of the serial data clock. In other words, a digital audio processing circuit capable of processing such large-bit, high-frequency digital data is also a further requirement. However, designing and installing such a circuit entails additional development time and development costs, which is disadvantageous.
Accordingly, it is an object of the present invention to provide an improved and useful optical signal processing circuit in which the above-described disadvantage is eliminated.
Another, further and more specific object of the present invention is to provide an improved and useful digital signal processing circuit capable of high-frequency sampling using a simple structure that minimizes incremental development costs.
The above-described objects of the present invention are achieved by a signal processing circuit for converting a 2-channel analog signal into a digital signal, the signal processing circuit comprising:
an analog/digital conversion component for sequentially converting the 2-channel analog signal into digital data according to a sampling clock; and
an operation control component for setting a high sampling frequency of the sampling clock at a frequency higher than a normal sampling frequency of the sampling clock and setting a sampling clock duty ratio so that digital data of at least one of the two channels can be sampled.
Additionally, the above-described objects of the present invention are also achieved by a signal processing circuit for converting 2-channel digital data into analog signals, the signal processing circuit comprising:
a digital/analog conversion component for sequentially converting the 2-channel digital data into analog signals according to a sampling clock; and
an operation control component for setting a high sampling frequency of the sampling clock at a frequency higher than a normal sampling frequency of the sampling clock and setting a sampling clock duty ratio so that digital data of at least one of the two channels can be sampled.
According to these aspects of the invention, high-frequency sampling of the A/D or D/A converted data is attained.